A Power-Efficient Design Approach to Radiation Hardened Digital Circuitry using Dynamically Selectable Triple Modulo Redundancy

Triple Modulo Redundancy (TMR) is one of the most common techniques for fault mitigation in digital systems. TMR-based computing has a natural application to mission critical systems for military and aerospace applications which are exposed to cosmic radiation and are susceptible to Single Event Upsets (SEUs). TMR’s increased immunity to SEUs comes at the expense of increased power consumption and area. This paper presents a dynamically selectable TMR architecture which can be used to reduce power consumption when radiation levels are low. We apply this architecture to a test system in order to evaluate its power reduction and area overhead compared to a traditional static TMR approach. We show that the dynamically selectable TMR can be adopted with only a 2.2% increase in equivalent gate count compared to the traditional static TMR when implemented on a Xilinx Virtex-4 FPGA. This approach yields as much as a 67% reduction in power consumption versus a traditional static TMR approach when radiation levels are low.